In this second part of the course we'll be exploring how barriers are typically implemented in hardware, and what the hardware is doing in response to software executing a barrier.

You'll learn:

• How Arm AMBA-based cache coherent interconnects work.

• How Shareability domains are typically defined in hardware.

• How barriers work when they're being broadcast onto the interconnect.

• How barriers work when they're instead being handled internally to the CPU.

Total runtime: 3 hours 10 minutes.