Barriers 101: Bundle
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Part 1: What are barriers, and why do we need them?

#1: Why weakly-ordered?
#2: System-level reordering
#3: Dependencies and successors
#4: Idempotence and speculation
#5: Data Memory Barriers
#6: Shareability domains
#7: Conventions and expectations
#8: Atomics and synchronization
#9: Workshop
#10a: Quiz
#10b: Quiz walkthrough
Part 2: How barriers work in hardware

#11: Interconnects and snoop requests
#12: Sequencing of coherent writes
#13: Defining Shareability domains in hardware
#14: Shareability on modern AMBA systems
#15: Broadcasting barriers onto the interconnect
#16: Distributed mesh network propagation
#17: DMA-capable peripheral devices
#18: Handling barriers internally to the CPU
#19a: Quiz
#19b: Quiz walkthrough
Part 3: Expanding our toolkit

#20: Implications of Arm's modified Harvard architecture
#21: Simulating barriers using herdtools
#22: DMB vs DSB in an Other-multi-copy atomic world
#23: Endpoint completion and control dependencies
#24a: Quiz
#24b: Quiz walkthrough
Part 4: Speculative side-channel attacks and break-before-make

#25: Speculative side-channel attacks
#26: Controlling speculation through barriers
#27: Break-before-make sequences
#28a: Quiz
#28b: Quiz walkthrough
#29: Arm Barriers 101 full course revision session

#2: System-level reordering

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