Bundle containing the complete Barriers 101 training course, a comprehensive deep dive into barriers in the Arm® Architecture:
Explore the rules underpinning Arm's weakly-ordered memory model.
Learn how to use barriers in software to manually enforce ordering.
Step through real examples of how barriers actually work in hardware.
Visualize memory accesses flowing through the interconnect fabric.
Gain confidence tackling new and unfamiliar barrier scenarios from first principles.
Also available as standalone parts: Part 1 | Part 2 | Part 3 | Part 4.
In this first part of the course we'll be exploring Arm's weakly-ordered memory model, in which memory accesses satisfying certain conditions are permitted to be freely reordered with respect to one another.
You'll learn:
Why Arm defines a weakly-ordered memory model.
The rules dictating whether two memory accesses are permitted to be reordered.
How to use barriers to manually enforce ordering between reorderable accesses.
How to descope barriers to mitigate any potential impacts on system performance.
Total runtime: 3 hours 14 mins.
In this second part of the course we'll be exploring how barriers are typically implemented in hardware, and what the hardware is doing in response to software executing a barrier.
You'll learn:
How Arm AMBA-based cache coherent interconnects work.
How Shareability domains are typically defined in hardware.
How barriers work when they're being broadcast onto the interconnect.
How barriers work when they're instead being handled internally to the CPU.
Total runtime: 3 hours 10 minutes.
In this third part of the course we'll be expanding our toolkit by exploring some of the more nuanced uses of barriers in the Arm Architecture.
You'll learn:
Why Data Memory Barriers are not always sufficient to guarantee ordering.
How to use other barriers to enforce ordering in those situations.
How Arm formally defines ordering relationships in its weakly-ordered memory model.
How to test for missing barriers under simulation.
Total runtime: 2 hours 27 minutes.
In this final part of the course we'll be exploring some of the more advanced cases for barriers in the Arm Architecture.
You'll learn:
How speculative side-channel attacks like Spectre and Meltdown work.
How we can use barriers to control speculation and to defend against these kinds of attacks.
How failing to correctly perform break-before-make sequences when making certain modifications to the page tables may lead to all sorts of nasty, horrible-to-debug issues.
How to use barriers to correctly perform such sequences.
Total runtime: 2 hours 53 minutes.
Our courses are suitable for all levels of experience, whether you're already a seasoned veteran or you're seeing barriers for the very first time.
We aim to go both broader and deeper than any other training platform; we show you how things really work, and more importantly, why.
Reinforce your learning with 120 multiple-choice questions spanning 4 quizzes, along with a barriers workshop and full course revision session.
We appreciate it can be difficult to balance training with your regular work; our courses come with lifetime access so you can learn at your own pace.
Try before you buy, and in the unlikely event that you're not entirely satisfied with your purchase then we'll refund you within the first 30 days.
We're proud to have a 100% 5⭐️ rating; see what our happy learners are saying:
"This is a great introductory course on Arm memory barriers. The instructor explains complex topics like weak memory ordering, instruction reordering, and barrier usage in a clear and structured manner. I especially appreciated the practical insights and real-world examples. It's a must-watch for anyone working close to hardware or writing low-level Arm code. Looking forward to the next parts in the series!"
"Part 2 covers AMBA interconnects and the two different ways how barriers can be dealt with in hardware. Note that this is not a training on AMBA architecture, but Ash instead makes a great didactical effort to only introduce as much of AMBA as needed to understand the interaction with barriers. In my opinion this is one of the strengths of Ash‘s way of teaching, which makes it easy to follow, even if there is no prior knowledge present."
"The material is presented with precise and thoughtful wording, and the examples are clear and easy to follow. The instructor does a great job of breaking down complex concepts into a logical, easy-to-understand flow."
Thank you for your courses on barriers. I’m really glad I got them - now I can study thinking, “Wow, barriers are cool - that’s why they built it this way,” instead of, “What else should I read to finally understand how it works?”
Ash Wilding, Founder
Ash previously lead Arm's global Architecture, Platforms and Open Source Software technical support and training organization.
There he acted as trusted advisor to some of Arm's biggest customers, and was one of Arm's lead technical trainers delivering courses on the Arm Architecture, Cortex-A / Neoverse-N CPUs, and supporting system fabric / peripherals, as well as Arm TrustZone technology.
Ash later joined the Amazon AWS EC2 Kernels & Operating Systems team, and more recently the Apple Platform Kernel team.
There he helped to develop and maintain the Arm Architecture and Apple CPU-specific layers of the XNU kernel running on all Apple devices, and also represented Kernel Engineering during the bring-up of several in-flight Apple Silicon designs, from pre-silicon simulation and FPGA through to prototype and production silicon tapeouts.